1. Field of the Invention
The present invention relates to an output circuit which is adapted for use in a semiconductor device, etc.
2. Description of the Related Art
There is a conventional output circuit as disclosed in Japanese Patent Laid-Open Publication No. 58-196726 (hereinafter referred to as a first reference) and Japanese Patent Laid-Open Publication No. 3-24820 (hereinafter referred to as a second reference). The first reference discloses two transistors connected in parallel with two output transistors which are serially connected between a power voltage and a ground voltage wherein operations of these two transistors are controlled by input and output signals of these two transistors when they are ANDed or ORed, thereby flowing a large load current so as to increase rise time of a power supply current. The second reference discloses a transistor connected in parallel with one of two output transistors which are serially connected between a power voltage and a ground voltage wherein an operation of the parallel connected transistor is controlled by an operation signals and its inverse operation signal of the output transistors when they are NORed, thereby suppressing ringing and speeding up access time.
There is also disclosed in the second reference that the outputs of the output transistors in the output circuit arc reset, namely, made in a high impedance state by a signal for deciding an output state of the output circuit.
The output signal of the output circuit has been recently required to be reset or be made in a high impedance state at high speed.